data brief for further information contact your local stmicroelectronics sales office. april 2009 rev 3 1/7 7 STI5162 low-cost interactive set-top box decoder features enhanced st20 32-bit vl-risc cpu unified memory interface ? up to 133 mhz, 16-bit wide sdr sdram, ? up to 166 mhz, 16-bit wide ddr sdram programmable flash memory interface demodulator compatible with i and q or if inputs for tuner interface channel management digital carrier, timing & symbol recovery loops decoding ? qpsk - 16 qam - 64 qam constellations mpeg-2 mp@ml video decoder graphics and display ? 3 display planes ? 2d paced blitter engine with fill function programmable transport interface (pti) ? single transport stream input for dvb central dma controller pal/ntsc/secam encoder ? rgb, cvbs, y/c and yuv outputs with four 10-bit dac outputs. audio subsystem ? simultaneous mpeg audio decode and output of dolby streams on s/pdif ? iec958/iec1937 digital audio output interface ? integrated stereo audio dac on-chip peripherals ? asc (uart) with tx and rx fifos ? 3 banks of 8-bit programmable i/o ? integrated vcxo jtag/tap interface package ? 15 mm x 15mm pbga240 0.8 mm pitch. 16 st20 c1 core 200 mhz dcu 4k icache 4k sram int controller 4k dcache audio decoder 16 audio dacs comms peripherals audio output audiol/r s/pdif 16 stbus interconnect video output rgb/yc/cvbs fdma ts in ts merger cofdm dvb/icam/des pti if pio ir rx 2x asc (uart) 2x ssc lmi pcm + s/pdif player comms block denc dvo bdisp gdma 8kb tile lcmpeg2 ddr/sdr sdram fmi + spi digital video nor flash www.st.com
description STI5162 2/7 1 description 1.1 general the STI5162 is the latest in the family of stbus set-top box ics providing high-performance, low-cost system-on-chip (soc) for mpeg processing in digital terrestrial stbs. it is derived from the sti5107, with the addition of a dvb-t cofdm demodulator and supports multiple platforms using a unified architecture. the STI5162 delivers enhanced performance with respect to previous devices. main memory is based upon a single 16-bit external sdr sdram or ddr dram. the display architecture of the devices is based upon a high performance blitter engine that supports clut8 and rgb16 formats for background, video and osd/graphics displays. it makes the porting of middleware easier with improved rendering. 1.2 applications figure 1. basic terrestrial tv stb the STI5162 is designed for low-cost basic stb applications. its bga package allows the use of a simple 2-layer pcb, with all signals and power supplies being routed through the top pcb layer. this leaves the bottom pcb layer dedicated to the ground plane and jtag connections. the STI5162 provides the following features: sdr and ddr sdram memory interface digital video output port (exclusive with parallel flash) serial flash interface for program storage serial ts input port two ascs (uarts) STI5162 vcr dvb-t rx tuner ir rx sdr cvbs yc+cvbs rgb or flash
STI5162 description 3/7 1.3 main features enhanced st20 32-bit vl-risc cpu ? 200-mhz, single cycle cache/4-kbyte instruction cache, 4-kbyte data cache, 4-kbyte sram local memory interface ? up to 133 mhz, 16-bit wide sdr sdram, ? up to 166 mhz, 16-bit wide ddr sdram programmable flash memory interface ? 3 separately configurable banks, 8/16-bits wide ? sram, peripheral, flash, sflash? support demodulator compatible with i and q or if inputs for tuner interface ? wide range carrier tracking loop for offset recovery ? dual analog to digital conversion ? signal strength indicator dedicated adc ? dual ? digital split agc for rf and bb channel management ? nordig unified specification (v1.0.2) capable ? dynamic fading compatible ? channel reception quality indicator ? out of guard interval echo synchronization ? impulsive noise rejection capable ? flexible fully-integrated digital channel filter with outstanding adjacent channel rejection capability digital carrier, timing & symbol recovery loops decoding ? 2 k, 4 k, 8 k fft length ? 5, 6, 7 and 8 mhz channel bandwidth ? 1/4, 1/8, 1/16, 1/32 guard interval length ? qpsk - 16 qam - 64 qam constellations ? hierarchical capability ? viterbi soft decoder rate 1/2 ? supports puncture rates 1/2, 2/3, 3/4, 5/6, 7/8 ? reed-solomon decoder ? energy dispersal descrambler programmable transport interface (pti) ? single transport stream input ? support for dvb transport streams ? integrated dvb, icam descramblers mpeg-2 mp@ml video decoder ? fully programmable horizontal and vertical srcs graphics and display ? 3 display planes
description STI5162 4/7 ? 8 bpp clut graphics, 256 x 30 bits (aycbcr) clut entries. 16 bpp true color graphics, rgb565, argb1555, argb4444 formats. link-list control ? alpha blending, antialiasing, antiflutter, antiflicker filters ? 2d paced blitter engine with fill function ? blitter based display compositor pal/ntsc/secam encoder ? rgb, cvbs, y/c and yuv outputs with four 10-bit dac outputs. rgb/cvbs or yuv/cvbs or yc/cvbs ? encoding of cgms closed caption, teletext, wss and vps audio subsystem ? mpeg-1 layers i/ii ? simultaneous mpeg audio decode and output of dolby streams on s/pdif ? iec958/iec1937 digital audio output interface ? integrated stereo audio dacs central dma controller on-chip peripherals ? asc (uart) with tx and rx fifos ? 3 banks of 8-bit programmable i/o ? spi for serial flash support ? 2 sscs for i 2 c/spi master/slave interfaces ? infrared receiver ? integrated vcxo ? low-power / rtc / watchdog controller ? flexible clock generation to operate with 4 mhz or 27 mhz external reference jtag/tap interface package ? 15mm x 15mm pbga240 0.8 mm pitch
STI5162 ordering information 5/7 2 ordering information table 1. ordering information order code packaging STI5162abb pbga240 15 mm x 15 mm
revision history STI5162 6/7 3 revision history table 2. document revision history date revision changes 09-march-2009 1 initial release 01-apr-2009 2 memory interface values updated. 10-apr-2009 3 memory interface (sdr sdram) new update.
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